Nanoarchitecture of a III-V semiconductor-on-silicon platform made by ion implantation and millisecond flash lamp annealing

The downscaling and stressor technology of Si based devices is extending the performance of the silicon channel to its limits. One solution for the performance progress which can overcome the downsizing limit in the silicon technology is the integration of different functional optoelectronic elements within one chip. For the on-chip optical interconnections a different material has to be used, e.g. a direct band gap III-V compound semiconductor material. Besides efficient light emission many of the binary semiconductors exhibit much larger carrier mobility than silicon. This feature is crucial for a further performance enhancement of advanced devices.
Recently we have demonstrated a compact, CMOS compatible and fully integrated solution for the integration of III-V semiconductor nanocrystals with silicon technology for optoelectronic applications. They are synthesized in silicon using combined ion beam implantation and millisecond flash lamp annealing (FLA) techniques [NanoLett. 11, 2814 (2011)]. FLA appears to be the most suitable technique for this purpose. The energy budget introduced to the sample during FLA is sufficient to recrystallize silicon amorphized during ion implantation and to form III-V nanocrystals (NCs) via the liquid phase processes. Microstructural, optical and electrical properties of III-V nanostructures (InAs, GaAs and InP) formed in silicon or on SOI wafers will be presented. The evolution of the III-V nanostructures growth during FLA and the influence of the annealing parameters on theirs crystallographic orientation, shape and size will be explored. Moreover, a self-organization of the III-V nano-objects on the SOI wafers after flashing will be presented. A unique nano-swelling effect appearing during ion implantation of the SOI wafers combined with millisecond range liquid phase epitaxy leads to the evolution of the III-V semiconductors from the quantum dots to the nano-films. Conventional selective etching was used to form the n-III-V/p-Si heterojunction. Current-voltage measurements confirm the heterojunction diode formation between n-type III-V quantum dots and p-type Si substrate. The main advantage of our method is its integration with large-scale silicon technology, which also allows applying it for Si-based self-powered photronic devices.