Top-down fabrication and characterization of reconfigurable silicon nanowire-based field effect transistors with Schottky contacts


Top-down fabrication and characterization of reconfigurable silicon nanowire-based field effect transistors with Schottky contacts

Deb, D.; Khan, M. B.; Georgiev, Y. M.; Löffler, M.; Weber, W.; Helm, M.; Erbe, A.

Abstract

In the last 60 years the size of a transistor has been reduced from few centimeters to few nanometers. Smarter, faster and cheaper: these are the three factors that motivated the miniaturization crusade in the silicon chip industry. Now we reach the end of physical scaling and it is expected that future development will be based on new ideas1: (i) new materials (high-mobility channel materials accompanied by metal gates with high-k gate dielectrics), (ii) new architectures (e.g. 3D integration), (iii) new functionality (e.g. reconfigurability), (iv) new computation principles (e.g. spintronics, quantum computing), etc.
In this work we deal with this problem by introducing reconfigurability in transistors. We report on characterization of reconfigurable, undoped silicon nanowire field effect transistors (FETs) with Schottky junctions fabricated on silicon on insulator (SOI) substrates by an industry compatible top-down process. Reconfigurable transistors employ an axial nanowire heterostructure (metal/intrinsic-silicon/metal) with independent gating of the two Schottky junctions and can be reversely configured as p-FET or n-FET simply by the application of an electric signal2.
The fabrication scheme is based on electron beam lithography (EBL) using hydrogen silsesquioxane (HSQ), a negative-tone electron beam resist, followed by inductively-coupled plasma (ICP) etching. The etch recipe was optimized with respect to selectivity, sidewall roughness and anisotropy by selecting an appropriate gas chemistry (SF6/C4F8) and controlling the ICP hardware parameters such as gas flow, mixed gas ratio, plasma power and chamber pressure. We produced silicon nanowires of 20 nm width and nanowire arrays with a pitch of ≈ 200 nm.
A nickel (Ni) layer of 50 nm thickness was sputtered on the Si nanowires at lithographically defined areas followed by lift-off and thermal annealing to create nickel-silicide Schottky junctions inside the nanowires. In this way, the source and drain regions were formed creating silicide-silicon-silicide contacts. Diffusion of Ni in Si nanowires was precisely controlled by the radial crystal orientation of the nanowires, which was checked by transmission electron microscopy (TEM). The Schottky junctions were electrostatically modulated by a back gate potential. Transport properties of these nanowires could be switched from p-type to n-type and vice-versa by changing the polarity of the back gate.

References
1. L. Risch, Solid-State Electronics. 50, 527 (2006).
2. A. Heinzig, T. Mikolajick, J. Trommer, D. Grimm and W. M. Weber, Nano Letters. 13, 4176 (2013).

Keywords: Nanowires; FETs; Schotky Junctions; Silicides

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Verknüpfte Publikationen

  • Vortrag (Konferenzbeitrag)
    ICSNN 2016 - 19th International Conference on Superlattices, Nanostructures and Nanodevices, 25.-29.07.2016, Hong Kong, China

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