Feasible device architectures for ultra-scaled CNTFETs

Feasible device architectures for ultra-scaled CNTFETs are studied down to 5.9 nm using a multiscale simulation approach covering electronic quantum transport simulations and TCAD numerical device simulations. Schottky-like and ohmic-like contacts are considered. The simplified approach employed in the numerical device simulator is critically evaluated and verified by means of comparing the results with electronic quantum simulation results of an identical device. Different performance indicators such as the switching speed, switching energy, the subthreshold slope, Ion/Ioff-ratio, among others, are extracted for different device architectures. These values guide the evaluation of the technology for different application scenarios. For high-performance logic applications, the buried gate CNTFET is claimed to be the most suitable structure.