CMOS compatible manufacturing of a hybrid SET-FET circuit

This study analyzes the CMOS compatibility in the manufacturing of a hybrid SET-FET circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar with embedded Si nanodot generated by ion-beam irradiation. The integration process from nanopillars to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs co-integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulation taking into account parasitic elements. The FET fabrication process is adapted to meet the requirements of the pre-fabricated nanopillars. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.