Strained GaAs nanowires with high electron mobility on Si substrates


Strained GaAs nanowires with high electron mobility on Si substrates

Balaghi, L.; Shan, S.; Fotev, I.; Moebus, F.; Rana, R.; Venanzi, T.; Hübner, R.; Mikolajick, T.; Schneider, H.; Helm, M.; Pashkin, O.; Dimakis, E.

Abstract

Novel transistor concepts based on semiconductor nanowires promise high performance, lower energy consumption and better integrability in various platforms in nanoscale dimensions. Concerning the intrinsic transport properties of electrons in nanowires, relatively high mobility values that approach those in bulk crystals have been obtained only in core/shell heterostructures, where electrons are confined inside the core and, thus, their scattering on the nanowire surface is suppressed.
Here, we demonstrate that the large strain in core/shell nanowires with significant lattice-mismatch between the core and the shell can affect the effective mass and the scattering of electrons in a way that boosts their mobility to higher levels compared to results obtained by any other means. Specifically, we use GaAs/InAlAs core/shell nanowires with a lattice mismatch in the range of 3%, grown on Si substrates by molecular beam epitaxy. Overgrown with an 80-nm-thick shell, the 22-nm-thick core is hydrostatically tensile-strained as found by both Raman scattering and photoluminescence measurements [1, 2]. The transport properties and dynamics of electrons were probed at room temperature by optical-pump THz-probe spectroscopy, which is an established contactless method that circumvents challenges in the fabrication of electrical contacts on nanowires. We found that the mobility of electrons inside the strained GaAs core undergoes a remarkable enhancement despite the small core thickness, becoming 30 – 50 % higher than in unstrained GaAs/AlGaAs nanowires or bulk GaAs [2]. Our studies are extended to modulation-doped GaAs/InAlAs nanowires and the results will be presented.
The reported strain-induced mobility enhancement is of major importance for the realization of transistors with high speed and low power consumption, having the potential to trigger major advancements in high-performance nanowire electronic devices monolithically integrated in Si platforms.

[1] L. Balaghi, G. Bussone, R. Grifone, R. Hübner, J. Grenzer, M. Ghorbani-Asl, A. V. Krasheninnikov, H. Schneider, M. Helm, E. Dimakis, Nat Commun 10, 2793 (2019).
[2] L. Balaghi, S. Shan, I. Fotev, F. Moebus, R. Rana, T. Venanzi, R. Hübner, T. Mikolajick, H. Schneider, M. Helm, A. Pashkin, E. Dimakis, Nat Commun 12, 6642 (2021).

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  • Lecture (Conference)
    19th Conference on Gettering and Defect Engineering in Semiconductor Technology, 10.09.2022, Mondsee, Austria

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