Publikationsrepositorium - Helmholtz-Zentrum Dresden-Rossendorf

Low-power logic and memory circuits remain a main task for the next generations of energy-efficient electronic devices. Single Electron Transistors (SETs) are extremely low energy dissipation devices. However, SETs operate usually at cryogenic temperatures and have some serious drawbacks. Fortunately, Field Effect Transistors (FETs) and SETs are
complementary: The SET is the champion of low-power consumption while FETs advantages, like high-speed, driving, voltage gain and input impedance can compensate exactly for SET's intrinsic drawbacks. To overcome the drawback of cryogenic temperature operation, each SET has to be manufactured with a quantum dot of a size of just a few nanometers, and this dot has to be located not more than about one nanometer apart from the electrodes. The large-scale implementation of SETs in room-temperature electronics is hampered by its unresolved manufacturability because such requirements are beyond the limits of present lithography. We employed self-organization to overcome the present-day limits of lithography. On 5…8nm thick SiO2 layers of (001)Si wafers about 30nm thick a-Si layers have been deposited and subsequently irradiated with 50 keV Si+ ions. The irradiation leads to ion beam mixing at the upper and lower Si/SiO2 interfaces and transforms the buried SiO2 layer to SiOx with x~1. Then, pillar arrays have been fabricated from such layer stacks using electron beam lithography and plasma etching. Arrays of pillars with different diameters from 100nm down to less than 20nm have been produced, where the smallest pillar diameters have been further reduced to ~10nm by plasma oxidation and selective oxide etching (sacrificial oxidation). In this manner we manufactured SiOx disks of ~10nm diameter and 5nm thickness sandwiched between the Si of the pillars. During Rapid Thermal Processing (RTP) of such pillars at 1050°C for 60s, phase separation SiOx  (1-x/2)Si + x/2SiO2 occurs via formation of Si nuclei and Ostwald ripening. Close to the SiO2/Si interfaces the Si excess of SiOx condensates on the upper/lower Si of the pillar, i.e. no Si nuclei can form there. The nucleation rate at the rim of the disk is reduced too, especially if there are traces of oxygen in the ambient. Thus, in nanopillars of ~10nm diameter a single Si dot of ~3nm forms in the ~5nm thick SiO2 disk, whereas in thicker pillars a few dots are found. From such nanopillars vertical nanowire Gate-All-Around SETs (nw GAA-SETs) are fabricated by gate oxide formation using plasma oxidation and gate layer deposition followed by contact formation. The nw GAA-SETs can be combined with nw GAA FETs to fabricate integrated hybrid SET/FET devices, where the FETs are responsible for current amplification.
The funding from the European Union’s Horizon 2020 research and innovation program under grand agreement Nº 688072 (project acronym: Ions4SET) is gratefully acknowledged.